Publikationsansicht

[Chu87] T.-A. Chu, Synthesis of Self-timed VLSI Circuits from Graph-theoretic (1986)

Abstract

[Boh95] M.T. Bohr, "Interconnect scaling-the real limiter to high performance ULSI,"

Details der Publikation

Download	http://citeseerx.ist.psu.edu/viewdoc/summary?doi=?doi=10.1.1.107.558
Quelle	http://www.bcim.lsbu.ac.uk/ccsv/SBU-CISM-02-18/Reference.pdf
Mitarbeiter	CiteSeerX
Archiv	CiteSeerX - Scientific Literature Digital Library and Search Engine (United States)
Typ	text
Sprache	Englisch