| SEAT-LA: A soft error analysis tool for combinational logic (2006) | |||||||||||||
Abstract | |||||||||||||
| this paper, we propose a new approach, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks | |||||||||||||
Details der Publikation | |||||||||||||
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