Corona: System Implications of Emerging Nanophotonic Technology (2009)
Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray Mclaren, Marco Fiorentino, Al Davis, ...
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and...
ACT:ALowPowerVLIWClusterCoprocessorforDSPApplications (2008)
Ali Ibrahim, Al Davis, Mike Parker
The ACT (Adaptive Cellular Telephony) coprocessor architecture is described and analyzed using a set of widely used DSP algorithms. Performance and power are compared to equivalent implementations on...
A Cluster Architecture for Embedded Perception (2008)
Binu Mathew, Al Davis, Mike Parker
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately the real-time performance requirements of complex perception...
Automating the Design of Embedded Domain Specific Accelerators (2008)
Domain specific architecture (DSA) design currently involves a lengthy process that requires significant designer knowledge, experience, and time in arriving at a suitable code generator and...
How Much Adaptivity is Required for Bursty Traffic? (2007)
Ludmila Cherkasova Al, Al Davis, Vadim Kotov, Ian Robinson, Tomas Rokicki
Deterministic routing strategies are cheap and fast to implement but suffer from increased message latency due to contention for resources in a packet switching fabric. Adaptive routing strategies...
Integrating user-level networks with smt (2007)
Mike Parker, Mike Parker, Al Davis, Al Davis, Wilson Hsieh, Wilson Hsieh
We describe a new architecture that improves message-passing performance, both for device I/O and for interprocessor communication. Our architecture integrates an SMT processor with a userlevel...
Approved for the Major Department (2007)
Eric Robert Peskin, Erik Brunvand, Al Davis, Ganesh Gopalakrishnan, Christian Schlegel, Thomas C. Henderson, ...
committee and by majority vote has been found to be satisfactory.
An Energy Efficient High Performance Scratch-pad Memory System (2007)
A low-power high-performance scratch-pad memory system for an embedded VLIW processor is presented. It uses a simple stream address generator capable of implementing a variety of addressing modes....
A Gaussian Probability Accelerator for SPHINX 3 (2007)
Binu K. Mathew, Al Davis, Zhen Fang
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech...
Application driven embedded system design: A face recognition case study (2007)
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core specialization has been...
Application driven embedded system design: A face recognition case study (2007)
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core specialization has been...
Approved for the Major Department (2006)
Zhen Fang, Rajeev Balasubramonian, Al Davis, Sally A. Mckee, Lixin Zhang, Martin Berzins, ...
submitted by
Address acceleration mechanisms for an adaptive cellular telephony processor (2005)
The computational complexity of cellular telephone standards has increased faster than Moore’s law. New architectural approaches will be needed in order to meet the performance needs while staying...
A low power architecture for embedded perception (2004)
Binu Mathew, Al Davis, Mike Parker
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of complex perception...
A Loop Accelerator for Low Power Embedded VLIW Processors (2004)
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performance. However,...
A characterization of visual feature recognition (2003)
Binu Mathew, Al Davis, Robert Evans
Natural human interfaces are a key to realizing the dream of ubiquitous computing. This implies that embedded systems must be capable of sophisticated perception tasks. This paper analyzes the nature...
A characterization of visual feature recognition (2003)
Binu Mathew, Al Davis, Robert Evans
Natural human interfaces are a key to realizing the dream of ubiquitous computing. This implies that embedded systems must be capable of sophisticated perception tasks. This paper analyzes the nature...
A Gaussian Probability Accelerator for SPHINX 3 (2003)
Binu K. Mathew, Al Davis, Zhen Fang
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech...
A Low-Power Accelerator for the SPHINX 3 Speech Recognition System (2003)
Binu Mathew, Al Davis, Zhen Fang
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech...
Efficient Remapping Mechanisms for an Adaptable Memory System (2002)
Lixin Zhang, Al Davis, Wilson Hsieh, Sally A. Mckee, Frederic T. Chong, Date John, ...
The speed gap between processors and memory continues to widen. This problem has led to an increased reliance on complex cache hierarchies. Caches are very eective for programs with near 100% cache...
Message-Passing for the 21st Century: Integrating User-Level Networks with SMT (2001)
Mike Parker, Al Davis, Wilson Hsieh
We describe a new architecture that improves message-passing performance, both for device I/O and for interprocessor communication. Our architecture integrates an SMT processor with a userlevel...
Design of a parallel vector access unit for SDRAM memory systems (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
We are attacking the memory bottleneck by building a “smart ” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting applications dictate how...
Profiling I/O Interrupts in Modern Architectures (2000)
Lambert Schaelicke, Al Davis, Sally A. Mckee
As applications grow increasingly communication-oriented, interrupt performance quickly becomes a crucial component of high performance I/O system design. At the same time, accurately measuring...
Algorithmic Foundations for a Parallel Vector Access Memory System (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access...
Design of a parallel vector access unit for SDRAM memory systems (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
We are attacking the memory bottleneck by building a “smart ” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting applications dictate how...
Design of a Parallel Vector Access Unit for SDRAM Memory Systems (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
We are attacking the memory bottleneck by building a "smart" memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting applications...
Algorithmic Foundations for a Parallel Vector Access Memory System (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor /memory performance gap for applications with strided access...
Algorithmic Foundations for a Parallel Vector Access Memory System (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor /memory performance gap for applications with strided access...
Algorithmic Foundations for a Parallel Vector Access Memory System (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access...
Algorithmic Foundations for a Parallel Vector Access Memory System (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access...
Design of a parallel vector access unit for SDRAM memory systems (2000)
Binu K. Mathew, Sally A. Mckee, John B. Carter, Al Davis
We are attacking the memory bottleneck by building a “smart ” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting applications dictate how...
Impulse: Building a smarter memory controller (1999)
John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, Erik Brunv, ...
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable...
Algorithms For Synthesis And Verification Of Timed Circuits And Systems (1999)
Wendy A. Belluomini, Wendy A. Belluomini, Erik Brunvand, Al Davis, Steven Burns, Ganesh Gopalakrishnan, ...
In order to increase performance, circuit designers are beginning to move away from traditional, synchronous designs based on static logic. Recent design examples have shown that significant...
Impulse: Building a Smarter Memory Controller (1999)
John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, Erik Brunvand, ...
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable...
Impulse: Building a Smarter Memory Controller (1999)
John Carter, Wilson Hsieh, Leigh Stoller, Mark Swanson, Lixin Zhang, Erik Brunvand, ...
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable...
Impulse: Building a Smarter Memory Controller (1999)
John Carter Wilson, Erik Brunv, Al Davis, Chen-chi Kuo, Ravindra Kuramkote, Michael Parker, ...
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable...
Impulse: Building a smarter memory controller (1999)
John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, Erik Brunv, ...
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable...
Memory system support for irregular applications (1998)
John Carter, Wilson Hsieh, Mark Swanson, Lixin Zhang, Erik Brunv, Al Davis, ...
Abstract. Because irregular applications have unpredictable memory access patterns, their performance is dominated by memory behavior. The Impulse con gurable memory controller will enable signi cant...
Memory System Support for Irregular Applications (1998)
John Carter, Wilson Hsieh, Mark Swanson, Al Davis, Michael Parker, Lambert Schaelicke, ...
Because irregular applications have unpredictable memory access patterns, their performance is dominated by memory behavior. The Impulse configurable memory controller will enable significant...
Impulse: An Adaptable Memory System (1998)
John Carter, Wilson Hsieh, Leigh Stoller, Mark Swanson, Lixin Zhang, Erik Brunvand, ...
This paper presents the Impulse adaptable memory system, which allows applications to make efficient use of cache space and bus bandwidth. Impulse has a configurable memory controller that allows...
Efficient Communication Mechanisms for Cluster Based Parallel Computing (1997)
Al Davis, Mark Swanson, Mike Parker
The key to crafting an effective scalable parallel computing system lies in minimizing the delays imposed by the system. Parallel algorithms must communicate frequently. The communication delay...
Efficient Communication Mechanisms for Cluster Based Parallel Computing (1996)
Al Davis, Mark Swanson, Mike Parker
. The key to crafting an effective scalable parallel computing system lies in minimizing the delays imposed by the system. Of particular importance are communications delays, since parallel...
Efficient Communication Mechanisms for Cluster Based Parallel Computing (1996)
Al Davis, Mark Swanson, Mike Parker
. The key to crafting an effective scalable parallel computing system lies in minimizing the delays imposed by the system. Of particular importance are communications delays, since parallel...
Avalanche: A Communication and Memory Architecture for Scalable Parallel Computing (1995)
John Carter Al, John B. Carter, John B. Carter, Al Davis, Al Davis, Ravindra Kuramkote, ...
As the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system...
Architecture for Scalable Parallel Computing (1995)
John Carter Al, John B. Carter, John B. Carter, Al Davis, Al Davis, Ravindra Kuramkote, ...
As the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system...
Avalanche: A Communication and Memory Architecture for Scalable Parallel Computing (1995)
John B. Carter, Al Davis, Ravindra Kuramkote, Chen-Chi Kuo, Leigh B. Stoller, Mark Swanson
As the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system...
The Post Office Experience: Designing a Large Asynchronous Chip (1993)
Al Davis, Ken Stevens, Bill Coates
The Post Office is an asynchronous, 300,000 transistor, full-custom CMOS chip designed as the communication component for the Mayfly scalable parallel processor. Performance requirements led to the...