Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology (2008)
Rousseau, Maxime, Rozeau, Olivier, Cibrario, Gérald, Le Carval, Gilles, Jaud, Marie-Anne, Leduc, Patrick, ...
Two parallel methods of simulation have been developed in order to evaluate the electrostatic impact that a through-silicon via (TSV) may have on a 65 nm MOS transistor. The first model is based on...
Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology (2008)
Rousseau, Maxime, Rozeau, Olivier, Cibrario, Gérald, Le Carval, Gilles, Jaud, Marie-Anne, Leduc, Patrick, ...
Two parallel methods of simulation have been developed in order to evaluate the electrostatic impact that a through-silicon via (TSV) may have on a 65 nm MOS transistor. The first model is based on...
Thermal modeling and management in ultrathin chip stack technology (2002)
Pinel, Stèphane, Marty, Antoine, Tasselli, Josiane, Bailbe, Jean-Pierre, Beyne, Eric, Van Hoof, Rita, ...
This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the...
Residual thermomechanical stresses in thinned-chip assemblies (2000)
Leseduarte Cuevas, Sergio, Marco Colás, Santiago, Beyne, Eric, Van Hoof, Rita, Marty, Antoine, Pinel, Stèphane, ...
A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this...