List Viterbi Decoding with Continuous Error Detection for Magnetic Recording (2009)
Dragan Petrović, Borivoje Nikolić, Kannan Ramch
arithmetic coding based continuous error detection (CED) scheme is applied to high-order partial-response magnetic recording channels. Commonly used magnetic recording systems employ...
High throughput lowdensity parity-check architectures (2009)
Engling Yeo, Payam Pakzad, Borivoje Nikolić, Venkat Anantharam
Abstract—Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC) decoders are presented. They are applied to codes with paritycheck matrices...
INVITED PAPER Embedding Mixed-Signal Design in Systems-on-Chip (2009)
Ali M. Niknejad, Borivoje Nikolić, Senior Member Ieee
Innovative approaches and new design methodologies are needed to integrate digital, analog and RF components in CMOS systems-on-a-chip smaller than 100 nm.
Rate 8/9 Sliding Block Distance-Enhancing Code with Stationary Detector (2009)
Abstract—A new distance-enhancing code for partial-response magnetic recording channels eliminates most frequent errors, while keeping the two-step code trellis time invariant. Recently, published...
Power and Area Minimization for Multidimensional Signal Processing (2009)
Dejan Marković, Borivoje Nikolić, Senior Member, Robert W. Brodersen
Abstract—Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing...
Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply (2009)
M. Vesterbacka, K. Palmkvist, L. Wanhammar, Dragan Maksimović, Vojin G. Oklobdžija, Borivoje Nikolić
[3] J. Pihl and E. J. Aas, “A 300 megasamples/s wave digital filter implementation
PHASE-LOCKED LOOP ARCHITECTURE FOR ADAPTIVE JITTER OPTIMIZATION (2008)
Socrates D. Vamvakos, Carl Werner, Borivoje Nikolić
A phase-locked loop (PLL) architecture is presented that allows adaptive optimization of tracking jitter by using an on-chip jitter estimation block. The jitter estimation circuit operates at the PLL...
Reduced Complexity Sequence Detection for High-Order Partial Response Channels (2008)
Michael Leung, Borivoje Nikolić, Taehyun Jeon
Abstract—Detector hardware complexity of high-order partial response magnetic read channels is a major obstacle to high data rate operation and reduced area and power consumption. The method...
INVITED PAPER Embedding Mixed-Signal Design in Systems-on-Chip (2008)
Ali M. Niknejad, Borivoje Nikolić, Senior Member Ieee
Innovative approaches and new design methodologies are needed to integrate digital, analog and RF components in CMOS systems-on-a-chip smaller than 100 nm.
Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply (2008)
M. Vesterbacka, K. Palmkvist, L. Wanhammar, Dragan Maksimović, Vojin G. Oklobdžija, Borivoje Nikolić
[3] J. Pihl and E. J. Aas, “A 300 megasamples/s wave digital filter implementation
List Viterbi Decoding with Continuous Error Detection for Magnetic Recording (2008)
Dragan Petrović, Borivoje Nikolić, Kannan Ramch
arithmetic coding based continuous error detection (CED) scheme is applied to high-order partial-response magnetic recording channels. Commonly used magnetic recording systems employ...
Hsin-i Liu, Vito Dai, Avideh Zakhor, Borivoje Nikolić
Future lithography systems must produce chips with smaller feature sizes, while maintaining throughput comparable to today’s optical lithography systems. This places stringent data handling...
Evaluation of the Low Frame Error Rate Performance of LDPC Codes Using Importance Sampling (2008)
Lara Dolecek, Zhengya Zhang, Martin Wainwright, Venkat Anantharam, Borivoje Nikolić
Abstract — We present an importance sampling method for the evaluation of the low frame error rate (FER) performance of LDPC codes under iterative decoding. It relies on a combinatorial...
Methods for True Energy-Performance Optimization (2008)
Dejan Markovic Student, Borivoje Nikolić, Mark A. Horowitz, Robert W. Brodersen
This paper presents methods for efficient energyperformance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the...
Quantization effects of low-density parity-check decoders (2007)
Zhengya Zhang, Lara Dolecek, Martin Wainwright, Venkat Anantharam, Borivoje Nikolić
Abstract−A class of combinatorial structures, called absorbing sets, strongly influences the performance of low-density paritycheck (LDPC) decoders. In particular, the quantization scheme strongly...
Analysis of absorbing sets for array-based LDPC codes (2007)
Lara Dolecek, Zhengya Zhang, Venkat Anantharam, Martin Wainwright, Borivoje Nikolić
Abstract — Low density parity check codes (LDPC) are known to perform very well under iterative decoding. However, these codes also exhibit a change in the slope of the bit error rate (BER) vs....
Zhengya Zhang, Lara Dolecek, Borivoje Nikolić, Venkat Anantharam, Martin Wainwright
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any structured LDPC code...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolić, Venkat Anantharam, Martin Wainwright
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any structured LDPC code...
Reduced complexity compression algorithms for direct-write maskless lithography systems (2006)
Hsin-i Liu, Vito Dai, Avideh Zakhor, Borivoje Nikolić
Achieving the throughput of one wafer layer per minute with a direct-write maskless lithography system, using 22 nm pixels for 45 nm feature sizes, requires data rates of about 12 Tb/s. In our...
Power-performance optimization for custom digital circuits (2005)
Radu Zlatanovici, Borivoje Nikolić
Abstract. This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to maximize the...
Layout Decompression Chip for Maskless Lithography (2004)
Borivoje Nikolić, Ben Wild, Vito Dai, Yashesh Shroff, Benjamin Warlick, Avideh Zakhor, ...
Future maskless lithography systems require data throughputs of the order of tens of terabits per second in order to have comparable performance to today’s mask-based lithography systems. This work...
A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR (2004)
Yun Chiu, Student Member, Paul R. Gray, Borivoje Nikolić
analog-to-digital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power...
Magnetic Recording Rob, Rob Lynch, Erozan M. Kurtas, Alex Kuznetsov, Engling Yeo, Borivoje Nikolić
The striking benefits of iterative detection have generated strong interest in the disk drive signal processing area, but thus far application of this technology has been rather limited. We review...
Least Mean Square Adaptive Digital Background (2004)
Calibration Of Pipelined, Yun Chiu, Cheongyuen W. Tsang, Student Member, Student Member, Borivoje Nikolić, ...
We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers...
Layout Decompression Chip for Maskless Lithography (2004)
Borivoje Nikolić, Ben Wild, Vito Dai, Yashesh Shroff, Benjamin Warlick, Avideh Zakhor, ...
Future maskless lithography systems require data throughputs of the order of tens of terabits per second in order to have comparable performance to today’s mask-based lithography systems. This work...
The search for a practical iterative detector for magnetic recording (2004)
Rob Lynch, Erozan Kurtas, Alex Kuznetsov, Engling Yeo, Borivoje Nikolić
As the difficulty in increasing areal recording densities rises, more attention is given to improvements available from advanced signal processing. A promising technique to achieve SNR improvement is...
Methods for true energy-performance optimization (2004)
Dejan Marković, Student Member, Vladimir Stojanović, Student Member, Borivoje Nikolić, Mark A. Horowitz, ...
This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the...
Kimmo Kuusilinna, Chen Chang, Hans-martin Bluethgen, W. Rhett, Brian Richards, Borivoje Nikolić, ...
Abstract: The productivity gap between the designer and the opportunities on silicon places increasing pressure particularly on system verification. A comprehensive design flow for digital systems...
A 500-Mb/s Soft-Output Viterbi Decoder (2003)
Engling Yeo Student, Engling Yeo, Stephanie A. Augsburger, Student Member, Student Member, W. Rhett Davis, ...
Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18- m CMOS technology. The throughput of the decoders is...
Fujio Ishihara Farhana, Fujio Ishihara, Farhana Sheikh, Borivoje Nikolić
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop...
A Shared-Well Dual-Supply-Voltage 64-bit ALU (2003)
Yasuhisa Shimazaki Member, Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolić
A shared n-well layout technique is developed for the design of dual-supply-voltage logic blocks. It is demonstrated on a design of a 64-bit arithmetic logic unit (ALU) module in domino logic. The...
Performance of deeply-scaled, power-constrained circuits (2003)
Borivoje Nikolić, Tsu-jae King
Power has become a primary design constraint in digital integrated circuits. Most designs in sub-100nm technologies will either maximize the performance under power constraints or minimize the energy...
Combining dual-supply, dual-threshold and transistor sizing for power reduction (2002)
Stephanie Augsburger, Borivoje Nikolić
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for evaluating the...
LIST VITERBI DECODING WITH CONTINUOUS ERROR DETECTION FOR MAGNETIC RECORDING (2001)
Dragan Petrović, Kannan Ramchandran, Borivoje Nikolić, Dragan Petrović
The List Viterbi Algorithm (LVA) with an arithmetic coding based continuous error detection (CED) scheme is applied to high-order partial-response magnetic recording channels. Commonly used magnetic...
High throughput low-density parity-check decoder architectures (2001)
Engling Yeo, Payam Pakzad, Borivoje Nikolić, Venkat Anantharam
Abstract—Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC) decoders are presented. They are applied to codes with paritycheck matrices...
VLSI Architectures for Iterative Decoders in Magnetic Recording Channels (2001)
Engling Yeo, Student Member, Payam Pakzad, Borivoje Nikolić, Venkat Anantharam
Abstract—VLSI implementation complexities of soft-input soft-output (SISO) decoders are discussed. These decoders are used in iterative algorithms based on Turbo codes or Low Density Parity Check...
Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements (2000)
Borivoje Nikolić, Vojin G. Oklobdˇzija, Vladimir Stojanović, Wenyan Jia
Abstract—Design and experimental evaluation of a new senseamplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF’s is the cross-coupled...