ITERATIVE PROCESSING: FROM APPLICATIONS TO PARALLEL IMPLEMENTATIONS (2009)
John M. Cioffi, Mark A. Horowitz, Ahmad R. Bahai
in my opinion, it is fully adequate
Vladimir Stojanovic, Dejan Markovic, Borivoje Nikolic, Mark A. Horowitz, Robert W. Brodersen
This paper relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption...
A 10-GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators (2008)
Student Member, C. Patrick Yue, Mark A. Horowitz, S. Simon Wong
Abstract—In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The...
High-Frequency Characterization of On-Chip Digital Interconnects (2008)
Bendik Klevel, Xiaoning Qi, Liam Madden, Takeshi Furusawa, Robert W. Dutton, Mark A. Horowitz, ...
Abstract—On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic...
A 4-ns 4K X l-bit Two-Port BiCMOS SRAM (2008)
Tsen-shau Yang, Student Member, Mark A. Horowitz, Bruce A. Wooley, He Time
Abstract —T’fris paper introduces a two-port BiCMOS static memory cell that combines ECL-level word-linevoltageswingsandemitter-follower bit-line coupling with a static CMOS latch for data...
A 10-GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators (2008)
Student Member, C. Patrick Yue, Mark A. Horowitz, S. Simon Wong
Abstract—In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The...
Time-Variant Characterization and Compensation of Wideband Circuits (2008)
Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Mark A. Horowitz
Abstract- Many wideband circuits use interleaving to extend bandwidth leaving them with a cyclically timevariant output. This paper describes a technique for characterization of these types of...
SP 25.7: Skew-Tolerant Domino Circuits (2008)
As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle time is increasing. Traditional domino circuits shown in Figure 1 are especially sensitive because...
Drew E. Wingard, Student Member, Don C. Stark, Student Member, Mark A. Horowitz
Abstract–The CMOS-storage emitter-access (CSEA) memory cell offers faster access than the MOS cells used in conventional BiCMOS SRAM’S, but using it in large memory arrays poses several problems....
Practical Limits of Multi-Tone Signaling over High-Speed Backplane Electrical Links (2008)
Amir Amirkhany, Aliazam Abbasfar, Vladimir Stojanović, Mark A. Horowitz
Abstract — Application of Discrete Multi-tone (DMT) signaling to high-speed backplane interconnects requires major modifications to the well-known analysis methods applied to wireline communication...
A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems (2008)
Jafar Savoj, Ali-azam Abbasfar, Amir Amirkhany, Mark A. Horowitz
In this paper, a new technique for characterization of digital-toanalog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs...
Vladimir Stojanovic, Dejan Markovic, Borivoje Nikolic, Mark A. Horowitz, Robert W. Brodersen
This paper relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption...
Methods for True Energy-Performance Optimization (2008)
Dejan Markovic Student, Borivoje Nikolić, Mark A. Horowitz, Robert W. Brodersen
This paper presents methods for efficient energyperformance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the...
Abstract Approximate Reachability with BDDs using Overlapping Projections (2007)
Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark A. Horowitz
Approximate reachability techniques trade o accuracy with the capacity to deal with bigger designs. Cho et al [3] proposed approximate FSM traversal algorithms over a partition of the set of state...
A 0.4-µm CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter (2007)
Ramin Farjad-Rad, Mark A. Horowitz, Thomas H. Lee
A serial link transmitter fabricated in a large-scale integrated 0.4-m CMOS process uses multilevel signaling (4PAM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI)...
a 0.8μm CMOS 2.5Gbps Oversampling Receiver and Transmitter for Serial Links (2007)
Mark A. Horowitz, Mark A. Horowitz
A receiver targeting OC-48 (2.488Gbps) serial data link has been designed and integrated in a 0.8µm CMOS process. An experimental receiving front end circuit demonstrates the viability of using...
OPTICAL INTERCONNECTS TO SILICON CHIPS USING SHORT PULSES (2007)
Joseph W. Goodman, Mark A. Horowitz
ii
1 Adaptive Supply Serial Links with sub-1V Operation and Per-pin Clock Recovery (2007)
As the number of high-speed links on a single chip continues to grow, the power dissipation of the link becomes as critical as its speed, leading to work in low power circuit structures [1] and...
SRT Division: Architectures, Models, and Implementations (2007)
David L. Harris, Stuart F. Oberman, Mark A. Horowitz
SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are...
Suggested Layout, SP25.7 SP25.7: Skew-Tolerant Domino Circuits (2007)
David Harris, Mark A. Horowitz
As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle time is increasing. Traditional domino circuits shown in Figure 1 are especially sensitive because...
WRITING, VERIFYING, AND EXPLOITING FORMAL SPECIFICATIONS FOR HARDWARE DESIGNS (2007)
Mark A. Horowitz, Dawson R. Engler
ii
Correspondence Address: (2007)
Mark A. Horowitz, Mark A. Horowitz, Thomas H. Lee, Thomas H. Lee, ...
Abstract — A serial link transmitter fabricated in the LSI 0.4-μm CMOS process uses multi-level signaling (4-PAM) and a 3-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by...
Abstract — A receiver targeting OC-48 (2.488Gbps) serial data link has been designed and integrated in a 0.8μm CMOS process. An experimental receiving front end circuit demonstrates the viability...
Mark A. Horowitz, Bruce A. Wooley
that I have read this dissertation and that in my opinion it is fully adequate,
A 0.8μm CMOS 2.5Gbps Oversampling Receiver for Serial Links * Correspondence Address: (2007)
Abstract — A receiver for OC-48 (2.488Gbps) serial data is designed using an 0.8μm CMOS process. Gate speed limitations are overcome using 1:8 demultiplexing at the receiver. To perform clock...
A 0.5- m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling (2007)
Ramin Farjad-rad, Student Member, Student Member, Mark A. Horowitz, Senior Member
Abstract—A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-"m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed...
Kluwar Academic Publishers, Clark Barrett, Jeremy Levitt, Jerry R. Burch, Automatic Verification, ...
f Computer Protocols, Prentice Hall Inc., 1991 15. Hiroaki Iwashita and Tsuneo Nakata, Forward Model Checking Techniques Oriented to Buggy Designs, IEEE International Conference on Computer Aided...
Cmos Image Sensors Dynamic Range and SNR Enhancement via Statistical Signal Processing (2007)
Xinqiao Liu, Abbas El Gamal, Mark A. Horowitz, Brian A. Wandell
Most of today's video and digital cameras use CCD image sensors, where the electric charge collected by the photodetector array during exposure time is serially shifted out of the sensor chip...
A Serial-Link Transceiver Based on 8-GSa/s A/D and D/A Converters in 0.25-μm CMOS (2007)
Vladimir Stojanovic, Vladimir Stojanovic, Siamak Modjtahedi, ...
Abstract — This paper presents a transceiver that uses a 4-bit flash ADC for the receiver and an 8-bit current-steering DAC for the transmitter. The 8-GSa/s converters are 8-way time interleaved....
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links,” GlobeCom (2006)
Amir Amirkhany, Vladimir Stojanović, Mark A. Horowitz
Abstract—A Multi-tone architecture is proposed for high-speed backplane serial links. To limit complexity, the links use analog multi-tone rather than the more modern DMT. The tradeoffs involved in...
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links,” GlobeCom (2006)
Amir Amirkhany, Aliazam Abbasfar, Vladimir Stojanović, Mark A. Horowitz
Abstract — Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This paper...
Digital Circuit Optimization via Geometric Programming (2005)
Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz
informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized...
Vladimir Stojanović, Andrew Ho, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, ...
Abstract—This paper describes an adaptively equalized, dualmode (PAM2 one-tap DFE/PAM4) 0.13 m CMOS transceiver chip, and the techniques used to continuously adapt the link. Interestingly, with...
Digital Circuit Optimization via Geometric Programming (2005)
Stephen P. Boyd, Seung Jean, Kim Dinesh, D. Patil, Mark A. Horowitz
This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex...
Circuits and techniques for high-resolution measurement of on-chip power supply noise (2005)
Elad Alon, Student Member, Vladimir Stojanović, Mark A. Horowitz
Abstract—This paper presents a technique for characterizing the statistical properties and spectrum of power supply noise using only two on-chip low-throughput samplers. The samplers utilize a...
Synergistic Caching in Single-Chip Multiprocessors (2005)
Leilani Harris, William James Dally, Mark A. Horowitz, Christos Kozyrakis
ii
Microsupercomputers: Design and Implementation (2004)
Hennessy, John L., Horowitz, Mark A.
Executive Summary: (1) Parallel Processor Architecture -- The primary focus of our architecture effort has been on completing the design of DASH and starting the construction of the prototype; (2)...
Microsupercomputers: Design and Implementation (2004)
Hennessy, John L., Horowitz, Mark A.
1. Executive Summary. A summary of progress for the period April 1989 through October 1989 follows: (1) Parallel Architecture: The Stanford DASH multiprocessor advances the state of parallel...
Microsupercomputers: Design and Implementation (2004)
Hennessy, John L., Horowitz, Mark A.
Project Goals: (1) Investigate fundamental properties of parallel programs and the implications for multiprocessor architectures and parallel programming and compilers; (2) Explore architectural...
Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz
A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others...
Vladimir Stojanović, Amir Amirkhany, Mark A. Horowitz
Abstract—Multi-Gb/s high-speed links face significant challenges in keeping up with the increase in desired data rates. In the evaluation of achievable data rates, it is necessary to include both...
DESIGN OF CMOS RECEIVERS FOR PARALLEL OPTICAL INTERCONNECTS (2004)
Mark A. Horowitz, Bruce A. Wooley
ii
Common-mode Backchannel Signaling System For Differential High-Speed Links (2004)
Andrew Ho, Vladimir Stojanović, Fred Chen, Carl Werner, Grace Tsang, Elad Alon, ...
Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell [1]. A...
Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver (2004)
Vladimir Stojanović, Andrew Ho, Fred Chen, Jason Wei, Elad Alon, Carl Werner, ...
To achieve high bit rates link designers are using more sophisticated communication techniques, often turning to 4PAM transmission or decision-feedback equalization (DFE). Interestingly, with only...
Vladimir Stojanović, Amir Amirkhany, Mark A. Horowitz
Abstract _-Multi-Gb/s high-speed links face significant challenges in keeping up with the increase in desired data rates. In the evaluation of achievable data rates, it is necessary to include both...
Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz
A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others...
Methods for true energy-performance optimization (2004)
Dejan Marković, Student Member, Vladimir Stojanović, Student Member, Borivoje Nikolić, Mark A. Horowitz, ...
This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the...
Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach (2003)
Jaeha Kim, Mark A. Horowitz, Gu-yeon Wei
Abstract—A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and...
10GHZ GLOBAL CLOCK DISTRIBUTION USING COUPLED STANDING-WAVE OSCILLATORS (2003)
that I have read this dissertation and that in my opinion it is fully adequate,
Charge Sharing Models for MOS Circuits. (2002)
Chu,Chorng-Yeong, Horowitz,Mark A.
This paper addresses timing and glitch detection problems involving charge sharing in acyclic resistor capacitor networks. Solutions to these problems are proposed and applied to real designs....
A Single Chip LSI High-Speed Functional Tester, (2002)
Miyamoto,Jun-ichi, Horowitz,Mark A.
A new architecture of single chip tester, DGR, will be proposed. It generates test vectors designated by the internal memory data, and simultaneously, detects the DUT data, being overwritten on that...
The light field video camera (2002)
Bennett Wilburn, Michal Smulski, Kelin Lee, Mark A. Horowitz
We present the Light Field Video Camera, an array of CMOS image sensors for video image based rendering applications. The device is designed to record a synchronized video dataset from over one...
Adaptive supply serial links with sub-1V operation and per-pin clock recovery (2002)
Jaeha Kim, Student Member, Mark A. Horowitz
Abstract—The application of adaptive power-supply regulation is extended to serial links. The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to...
Methods for true power minimization (2002)
Robert W. Brodersen, Mark A. Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These...
Vladimir Stojanovic, Dejan Markovic, Borivoje Nikolic, Mark A. Horowitz, Robert W. Brodersen
This paper relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption...
Methods for true power minimization (2002)
Robert W. Brodersen, Mark A. Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These...
Adaptive supply serial links with sub-1V operation and per-pin clock recovery (2002)
Jaeha Kim, Mark A. Horowitz, Full Vdd, Full Vdd, V Vctrl
As the number of high-speed links on a single chip continues to grow, the power dissipation of the link becomes as critical as its speed, leading to work in low power circuit structures [1] and...
Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver (2002)
Vladimir Stojanovic, George Ginis, Mark A. Horowitz
Abstract-Time Division Multiplexing (TDM) must be employed in multi-GSa/s transceivers in order to overcome onchip clock frequency limitations. This paper describes a transmit pre-emphasis filter for...
An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation (2001)
Jaeha Kim, Student Member, Mark A. Horowitz
Abstract—We propose a digital controller for adaptive power-supply regulation that uses sliding control, which is a widely used technique in switching power supplies for its fast transient response...
Fast low-power decoders for RAMs (2001)
Bharadwaj S. Amrutur, Mark A. Horowitz
Abstract—Decoder design involves choosing the optimal circuit style and figuring out their sizing, including adding buffers if necessary. The problem of sizing a simple chain of logic gates has an...
An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation (2001)
Jaeha Kim, Student Member, Mark A. Horowitz
Abstract---We propose a digital controller for adaptive power-supply regulation that uses sliding control, which is a widely used technique in switching power supplies for its fast transient response...
Ron Ho, Kenneth W. Mai, Student Member, Mark A. Horowitz
This paper examines wire and gate delays as technologies migrate from 0.18-m to 0.035-m feature sizes to better understand the magnitude of the wiring problem. Wires that shorten in length as...
A variable-frequency parallel I/O interface with adaptive power-supply regulation (2000)
Gu-yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz
Abstract—This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters...
A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation (2000)
Evelina Yeung, Student Member, Mark A. Horowitz
Abstract—This paper describes voltage and timing margins and design trade-offs in low-cost parallel links. Results from a transceiver prototype demonstrate that per-pin skew compensation improves...
A variable-frequency parallel I/O interface with adaptive power-supply regulation (2000)
Gu-yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz
Abstract—This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters...
A 0.3 "m CMOS 8-Gb/s 4-PAM serial link transceiver (2000)
Ramin Farjad-rad, Student Member, Mark A. Horowitz, Thomas H. Lee
Abstract—An 8-Gb/s 0.3- m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel...
Microsupercomputers: Design and Implementation. (1998)
Hennessy, John L., Horowitz, Mark A.
Contents: 1) Parallel Processor Architecture; 2) Parallel Software; 3) Computer-Aided Design (CAD) Tools; and 4) VLSI. Keywords: Multiprocessors; Computerized simulation; Very large scale integrated...
Microsupercomputers: Design and Implementation. (1998)
Hennessy, John L., Horowitz, Mark A.
This report design and use of micro-super-computers. Keywords: Parallel processors; Parallel processing; Computer hardware; Computer programs; Stream processing; Computer Aided design; Computerized...
SPIM (Stanford Pipelined Iterative Multiplier): A Pipelined 64 X 64 Bit Iterative Multiplier, (1998)
Santoro, Mark R., Horowitz, Mark A.
A 64 by 64 bit iterating multiplier, SPIM (Stanford Pipelined Iterative Multiplier) is presented. The pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a...
Microsupercomputers: Design and Implementation. (1998)
Hennessy, John L., Horowitz, Mark A.
Contents: (1) Parallel processor architecture; (2) Parallel software; (3) Unit processor architecture; (4) Computer aided designs tools; (5) Very large scale integration. Keywords: Scalable shared...
Microsupercomputers: Design and Implementation. (1998)
Hennessy, John L., Horowitz, Mark A.
Table of Contents: (1) Executive Summary, Goals and Accomplishments; (2) Technical Progress - 2.1 Parallel Processor Architecture; 2.2 Parallel Software; 2.3 Uniprocessor Architecture; 2.4 Computer...
Microsupercomputers: Design and Implementation. (1998)
Hennessy, John L., Horowitz, Mark A.
This research project was to explore and develop the technologies necessary to build high performance computers from low-cost VLSI-based microprocessors. The project embraced a wide set of...
A Directory-Based Scalable General-Purpose Shared-Memory Multiprocessor (1998)
Hennessy, John L., Horowitz, Mark A.
This research focused on the design and development of scalable shared-memory machines, in particular, those using directory-based cache coherence. This research led to the design and fabrication of...
Approximate Reachability With BDDs Using Overlapping Projections (1998)
Govindaraju, Shankar G., Dill, David L., Hu, Alan J., Horowitz, Mark A.
Approximate reachability techniques trade off accuracy with the capacity to deal with bigger designs. Cho et al proposed approximate FSM traversal algorithms over a partition of the set of state...
The Light Field Video Camera (1998)
Wilburn, Bennett, Smulski, Michal, Lee, Kelin, Horowitz, Mark A.
We present the Light Field Video Camera, an array of CMOS image sensors for video image based rendering applications. The device is designed to record a synchronized video dataset from over one...
Low-power SRAM design using half-swing pulse-mode techniques (1998)
Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, ...
Abstract—This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM...
A Replica Technique for Wordline and Sense Control in Low-power SRAMs (1998)
Bharadwaj S. Amrutur, Mark A. Horowitz, Senior Member
Abstract — With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications...
Approximate Reachability with BDDs using Overlapping Projections (1998)
Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark A. Horowitz
Approximate reachability techniques trade off accuracy with the capacity to deal with bigger designs. Cho et al [3] proposed approximate FSM traversal algorithms over a partition of the set of state...
Supply and threshold voltage scaling for low power CMOS (1997)
Ricardo Gonzalez, Benjamin M. Gordon, Mark A. Horowitz
Abstract — This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS...
A Semidigital Dual Delay-Locked Loop (1997)
Stefanos Sidiropoulos, Student Member, Mark A. Horowitz, Senior Member
Abstract—This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2%) phase shift, and large operating range. The architecture employs a core loop to...
Skew-Tolerant Domino Circuits (1997)
David Harris, Student Member, Mark A. Horowitz, Senior Member
Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the...
SRT division architectures and implementations (1997)
David L. Harris, Stuart F. Oberman, Mark A. Horowitz
SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are...
SRT division architectures and implementations (1997)
David L. Harris, Stuart F. Oberman, Mark A. Horowitz
SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are...
Stefanos Sidiropoulos, Mark A. Horowitz
gure 2 shows a more detailed diagram of the DLL. To reduce clock jitter, all the clock paths are differential. In order to minimize dynamic supply sensitivity this design uses a separate differential...
Skew-Tolerant Domino Circuits (1997)
David Harris, Mark A. Horowitz
This paper describes a methodology which boosts operating frequency by tolerating clock skew, eliminating latches from the critical path, and better balancing logic between phases of the pipeline....
Skew-Tolerant Domino Circuits (1997)
David Harris, Student Member, Mark A. Horowitz, Senior Member
Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the...
Supply and threshold voltage scaling for low power CMOS (1997)
Ricardo Gonzalez, Benjamin M. Gordon, Mark A. Horowitz
Abstract — This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS...
Architecture validation for processors (1995)
Richard C. Ho, C. Han Yang, Mark A. Horowitz, David L. Dill
Modern, high performance microprocessors are extremely complex machines which require substantial validation effort to ensure functional correctness prior to tapeout. Generating the corner cases to...
A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider (1991)
Ted E. Williams, Student Member, Mark A. Horowitz
Abstract-This paper describes the design of a custom inte-grated circuit for the arithmetic operation of division. The chip uses self-timing to avoid the need for high-speed clocks, and directly...
A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider (1991)
Ted E. Williams, Student Member, Mark A. Horowitz
Abstroct—This paper describes the design of a custom integrated circuit for the arithmetic operation of division. The chip uses self-timing to avoid the need for high-speed clocks, and directly...
A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider (1991)
Ted E. Williams, Student Member, Mark A. Horowitz
Abstroct—This paper describes the design of a custom integrated circuit for the arithmetic operation of division. The chip uses self-timing to avoid the need for high-speed clocks, and directly...
Boosting beyond static scheduling in a superscalar processor (1990)
Michael D. Smith, Monica S. Lam, Mark A. Horowitz
Superscalar processors are uniprocessor organizations capable of increasing machine performance by executing multiple scalar instructions in parallel. Since the amount of instruction-level...
A 4-ns BiCMOS Translation-Lookaside Buffer (1990)
Leilani R. Tamura, Tsen-shau Yang, Drew E. Wingard, Mark A. Horowitz, Andbruce A. Wooley
Abstract —A translation-lookaside buffer (TLB) plays an integral role in virtual memory management by providing fast virtual-to-physical address translations. This paper describes a 64-entry, fully...
Limits on Multiple Instruction Issue (1989)
Michael D. Smith, Mike Johnson, Mark A. Horowitz
The performance of microprocessors has increased dramatically over the past few years. Part of the performance gain has come from reducing the cycle time, while the rest has come from decreasing the...
Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver (1934)
Vladimir Stojanovic, George Ginis, Mark A. Horowitz
Abstract-Time Division Multiplexing (TDM) must be employed in multi-GSa/s transceivers in order to overcome onchip clock frequency limitations. This paper describes a transmit pre-emphasis filter for...