Abstract Control CPR: A Branch Height Reduction Optimization for EPIC Architectures (2008)
Michael Schlansker, Scott Mahlke, Richard Johnson
The challenge of exploiting high degrees of instruction-level parallelism is often hampered by frequent branching. Both exposed branch latency and low branch throughput can restrict parallelism....
ACRES Architecture and Compilation (2007)
Boon Seong Ang, Boon Seong Ang, Michael Schlansker, Michael Schlansker
reconfigurable computing, spatial compilation, pipelined interconnect, distributed control, remote branch architecture, reconfigurable memory High-performance computing engines often provide...
A distributed control path architecture for vliw processors (2005)
Hongtao Zhong, Scott Mahlke, Michael Schlansker
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that they do not scale...
A Distributed Control Path Architecture (2005)
For Vliw Processors, Hongtao Zhong, Kevin Fan, Scott Mahlke, Michael Schlansker
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that they do not scale...
Link Capacity Control in a Computer Communication Network. (2002)
Schlansker,Michael, Chou,Timothy
This paper describes a line switching communication network where, as the network becomes congested, additional lines are opened to relieve congestion. It is assumed that a fixed charge is paid for...
Bitwidth sensitive code generation in a custom embedded accelerator design system (2001)
Scott Mahlke, Rajiv Ravindran, Michael Schlansker, Robert Schreiber, Timothy Sherwood
An ever larger variety of embedded ASICs is being designed and deployed to satisfy an explosively growing demand for new
Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators (2001)
Scott Mahlke, Rajiv Ravindran, Michael Schlansker, Robert Schreiber, Timothy Sherwood
applicationspecific design, architecture synthesis, bitwidth, clustering, embedded system, hardware accelerator, operation scheduling, resource allocation PICO is a system for automatically...
Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators (2001)
Scott Mahlke, Rajiv Ravindran, Michael Schlansker, Robert Schreiber, Timothy Sherwood
application-speci c design, architecture synthesis, bitwidth, clustering, embedded system, hardware accelerator, operation scheduling, resource allocation PICO is a system for automatically...
Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators (2001)
Scott Mahlke, Rajiv Ravindran, Michael Schlansker, Robert Schreiber, Timothy Sherwood
PICO is a system for automatically synthesizing embedded hardware accelerators from loop nests speci ed in the C programming language. A key issue confronted when designing such accelerators is the...
Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators (2001)
Scott Mahlke, Rajiv Ravindran, Michael Schlansker, Robert Schreiber, Timothy Sherwood
Abstract—Program-in chip-out (PICO) is a system for automatically synthesizing embedded hardware accelerators from loop nests specified in the C programming language. A key issue confronted when...
Control CPR: A Branch Height Reduction Optimization for EPIC Architectures (1999)
Michael Schlansker, Scott Mahlke, Richard Johnson
The challenge of exploiting high degrees of instruction-level parallelism is often hampered by frequent branching. Both exposed branch latency and low branch throughput can restrict parallelism....
Control CPR: A branch height reduction optimization for EPIC architectures (1999)
Michael Schlansker, Michael Schlansker, Scott Mahlke, Scott Mahlke, Richard Johnson, Richard Johnson
ILP, critical path reduction, compilers © Copyright Hewlett-Packard Company 1999 The challenge of exploiting high degrees of instructionlevel parallelism is often hampered by frequent branching....
Parallelization of control recurrences for ILP processors (1996)
Michael Schlansker, Vinod Kathail, Sadun Anik
The performance of applications executing on processors with instruction level parallelism is often limited by control and data dependences. Performance bottlenecks caused by dependences can...
Global Predicate Analysis and its Application to Register Allocation (1996)
David Gillies, Richard Johnson, Ju Richard Johnson, Michael Schlansker
To fully utilize the wide machine resources in modern high-performance microprocessors it is necessary to exploit parallelism beyond individual basic blocks. Architectural support for predicated...
Michael Schlansker, Vinod Kathail
This report describes parallelization techniques for accelerating a broad class of recurrences on processors with instruction level parallelism. We introduce a new technique, called blocked...
Acceleration of Algebraic Recurrences on Processors with Instruction Level Parallelism (1993)
Michael Schlansker, Vinod Kathail
Architectures with instruction level parallelism such as VLIW and superscalar processors provide parallelism in the form of a limited number of pipelined functional units. For these architectures,...
Parallelization of loops with exits on pipelined architectures (1990)
Parthasarathy Tirumalai, Meng Lee, Michael Schlansker, P. Tirumalai, M. Lee, M. Schlansker
conditional execution; dependence graphs; loop scheduling; modulo scheduling; performance bounds; pipelined architectures; software pipelining; while loops To be published inthe proceedings of...