HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction (2008)
Phil May, Santithorn Bunchua, Student Member, D. Scott Wills, Senior Member
Abstract—Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communicate at...
The Reconfigurable Streaming Vector Processor (RSVP™) (2007)
Silviu Ciricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, ...
The need to process multimedia data places large computational demands on portable/embedded devices. These multimedia functions share common characteristics: they are computationally intensive and...
Phil May, Jeffrey Cross, Abelardo Lopez-lagunas, Brent Buchanan, D. Scott Wills, Nan Marie Jokerst, ...
Abstract—This letter presents testing results of an integrated optoelectronic (OE) channel employing hop-by-hop error control circuitry based on cyclic redundancy codes (CRC) to improve the...
Processing Architectures for Smart Pixel Systems (1996)
Scott Wills, James M. Baker, Huy H. Cat, Sek Chai, Jos� Cruz-rivera, John Eble, ...
Smart pixel architectures offer important new opportunities for low cost, portable image processing systems. They provide greater I/O bandwidth and computing performance than systems based on CCD and...
Future Branches -- Beyond Speculative Execution
Bill Appelbe, Reid Harmon, Maurizio Vitale, Sri Doddapaneni, Phil May, Scott Wills
. The performance and hardware complexity of superscalar architectures is hindered by conditional branch instructions. When conditional branches are encountered in a program, the instruction fetch...