Jérôme Waldispühl, Srinivas Devadas, Bonnie Berger, Peter Clote, W Ucuacggccagc
• ab-initio prediction (does not require homolog), • single structure prediction. Partition function and base pair binding probabilities (McCaskill,1990). UCUCAAACCAGA • evaluate the ensemble...
Guaranteed in-order packet delivery using Exclusive Dynamic Virtual Channel Allocation (2009)
Devadas, Srinivas, Cho, Myong Hyon, Shim, Keun Sup, Lis, Mieszko
In-order packet delivery, a critical abstraction for many higher-level protocols, can severely limit the performance potential in low-latency networks (common, for example, in network-on-chip designs...
Partitioning Strategies for Concurrent Programming (2009)
Devadas, Srinivas, Agarwal, Anant, Hoffmann, Henry
This work presents four partitioning strategies, or patterns, useful for decomposing a serial application into multiple concurrently executing parts. These partitioning strategies augment the...
Partitioning Strategies for Concurrent Programming (2009)
Devadas, Srinivas, Agarwal, Anant, Hoffmann, Henry
This work presents four partitioning strategies, or patterns, useful for decomposing a serial application into multiple concurrently executing parts. These partitioning strategies augment the...
The Trusted Execution Module: Commodity General-Purpose Trusted Computing (2009)
Victor Costan, Marten Van Dijk, Srinivas Devadas
Abstract. This paper introduces the Trusted Execution Module (TEM); a high-level specification for a commodity chip that can execute usersupplied procedures in a trusted environment. The TEM is...
Diastolic Arrays: Throughput-Driven Reconfigurable Computing (2009)
Myong Hyon Cho, Chih-chi Cheng, Michel Kinsy, G. Edward Suh, Srinivas Devadas
Abstract — Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues. FIFO virtualization units enable relaxed timing of data...
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks (2009)
Kinsy, Michel, Wen, Tina, Shim, Keun Sup, Lis, Mieszko, Cho, Myong Hyon, Devadas, Srinivas
Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-routing flows, but...
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks (2009)
Kinsy, Michel, Wen, Tina, Shim, Keun Sup, Lis, Mieszko, Cho, Myong Hyon, Devadas, Srinivas
Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-routing flows, but...
Precomputation-Based Sequential Logic Optimization (2009)
For Low Power, Mazhar Alidina, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou
Abstract We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the...
Access-Controlled Resource Discovery (2009)
Matthew Burnside, Dwaine Clarke, Sanjay Raman, Srinivas Devadas, Ronald Rivest
Introduction: Resource discovery is one of the fundamental challenges that must be faced in the context of pervasive computing. The dynamic nature of pervasive networks makes it difficult for users...
RNAmutants: a web server to explore the mutational landscape of RNA secondary structures (2009)
Waldispühl, Jerome, Devadas, Srinivas, Berger, Bonnie, Clote, Peter
The history and mechanism of molecular evolution in DNA have been greatly elucidated by contributions from genetics, probability theory and bioinformatics—indeed, mathematical developments such as...
Efficient stochastic simulation of reaction-diffusion processes via direct compilation (2009)
Lis, Mieszko, Artyomov, Maxim N., Devadas, Srinivas, Chakraborty, Arup K.
We present the Stochastic Simulator Compiler (SSC), a tool for exact stochastic simulations of well-mixed and spatially heterogeneous systems. SSC is the first tool to allow a readable high-level...
ABSTRACT Offline Count-Limited Certificates ∗ (2008)
Marten Van Dijk, Jonathan Rhodes, Srinivas Devadas
In this paper, we present the idea of offline count-limited certificates (or clics for short), and show how these can be implemented using minimal trusted hardware functionality already widely...
Analytical Cache Models with Applicationsto Cache Partitioning (2008)
G. Edward Suh, Srinivas Devadas, Larry Rudolphlaboratory, Computer Science
Blaise Gassend, Daihyun Lim, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas, Prof Holstlaan Eindhoven
This paper describes a technique to reliably and securely identify individual integrated circuits (ICs) based on the precise measurement of circuit delays and a simple challenge–response protocol....
Srinivas Devadas, Kurt Keutzer, Richard Newton
netlist logic optimization netlist physical design layout
ABSTRACT Secure Program Execution via Dynamic Information Flow Tracking (2008)
G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas
We present a simple architectural mechanism called dynamic information flow tracking that can significantly improve the security of computing systems with negligible performance overhead. Dynamic...
AEGIS – Tamper Evident and Tamper Resistant Processing (2008)
G. Edward Suh, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas, Tal Garfinkel, Ben Pfaff, ...
Trusted computing means that the computer will consistently behave in specific ways, and those behaviors will be enforced by hardware and software. Enlightened after reading the papers: Trusted...
Learning Biophysically-Motivated Parameters for Alpha Helix Prediction (2008)
Blaise Gassend, Charles W. O’donnell, William Thies, Andrew Lee, Marten Van Dijk, Srinivas Devadas
Background: Our goal is to develop a state-of-the-art protein secondary structure predictor, with an intuitive and biophysically-motivated energy model. We treat structure prediction as an...
Farzan Fallah, Srinivas Devadas
Functional simulation is still the primary workhorse for ver-ifying the functional correctness of hardware designs. Func-tional verification is necessarily incomplete because it is not...
Learning Biophysically-Motivated Parameters for Alpha Helix Prediction (2008)
Blaise Gassend, Charles W. O’donnell, William Thies, Andrew Lee, Marten Van Dijk, Srinivas Devadas
support vector machines, dynamic programming
Offline Untrusted Storage with Immediate Detection of Forking and Replay Attacks ∗ ABSTRACT (2008)
Marten Van Dijk, Jonathan Rhodes, Srinivas Devadas
We address the problem of using an untrusted server with only a trusted timestamping device (TTD) to provide trusted storage for a large number of clients, where each client may own and use several...
Abstract Performance-driven Synthesis of Asynchronous Controllers (2008)
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) — representations of logic...
Blaise Gassend, Charles W. O’donnell, William Thies, Andrew Lee, Marten Van Dijk, Srinivas Devadas
Our goal is to create an accurate protein secondary structure predictor based on an intuitive and biophysically-motivated energy model Secondary structures are determined by a prediction algorithm...
ABSTRACT Silicon Physical Random Functions (2008)
Blaise Gassend, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas, Blaise Gassend, Dwaine Clarke, ...
We describe the notion of a Physical Random Function (PUF). We argue that a complex integrated circuit can be viewed as a silicon PUF and describe a technique to identify and authenticate individual...
Matt Burnside, Dwaine Clarke, Blaise Gassend, Thomas Kotwal, Marten Van Dijk, Srinivas Devadas, ...
Introduction: The use of computers in public places is increasingly common in everyday life. In using one of these computers, a user is trusting it to correctly carry out her orders. For many...
Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten Van Dijk, Srinivas Devadas
Abstract—Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering...
ABSTRACT Secure Program Execution via Dynamic Information Flow Tracking (2008)
G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas
We present a simple architectural mechanism called dynamic information flow tracking that can significantly improve the security of computing systems with negligible performance overhead. Dynamic...
Blaise Gassend, Charles W. O’donnell, William Thies, Andrew Lee, Marten Van Dijk, Srinivas Devadas
Abstract. Our goal is to develop a state-of-the-art secondary structure predictor with an intuitive and biophysically-motivated energy model through the use of Hidden Markov Support Vector Machines...
Learning Biophysically-Motivated Parameters for Alpha Helix Prediction (2008)
Blaise Gassend, Charles W. O’donnell, William Thies, Andrew Lee, Marten Van Dijk, Srinivas Devadas
support vector machines, dynamic programming
Power Estimation Under User-Specified Input (2008)
Sequences And Programs, José Monteiro, R. Alves Redol, Srinivas Devadas
We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable...
George Hadjiyiannis, Silvina Hanono, Srinivas Devadas
Abstract — We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features and flexibility...
Precomputation-Based Sequential Logic Optimization (2007)
For Low Power, Mazhar Alidina, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output...
An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis (2007)
Srinivas Devadas, Kurt Keutzer
Most approaches to the synthesis of built-in self test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BIST generator is chosenandthen evaluatedby faultsimulating the...
Offline Authentication of Untrusted Storage (2007)
Dwaine Clarke, Blaise Gassend, G. Edward Suh, Marten Van Dijk, Srinivas Devadas
We extend the offline memory correctness checking scheme presented by Blum et. al [BEG + 91], by using incremental cryptography, to detect attacks by an active adversary. We also introduce a hybrid...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of...
Delay-Based Circuit Authentication With Application to Key Cards (2007)
Blaise Gassend, Dwaine Clarke, Marten Dijk, Srinivas Devadas
Srinivas Devadas, Kurt Keutzer, Jacob White
The high transistor density now possible with CMOS integrated circuits has made power dissipation an important design consideration. However, power dissipation in a logic cir-cuit is a function of...
Combinational Circuits Using Boolean Function Manipulation (2007)
Srinivas Devadas, Kurt Keutzer, Jacob White, Associate Member
Abstract--Estimating maximum power dissipation for a CMOS logic network is difficult because the power dissipated by the network is typically a strong function of the network's inputs. This...
Code Generation and Optimziation Techniques for Embedded Digital Signal Processors (2007)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, ...
The advent of 0.5 processing that allows for the integration of 5 million transistors on a single integrated circuit has brought forth new challenges and opportunities in embedded-system design. This...
José Monteiro, Srinivas Devadas, Kurt Keutzer, Jacob White
Abstract—We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for...
José Monteiro, Srinivas Devadas, Abhijit Ghosh
Abstract — Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a logic circuit, thereby reducing switching activity and power dissipation,...
Learning biophysically-motivated parameters for alpha helix prediction (2007)
Gassend, Blaise, O'Donnell, Charles W, Thies, William, Lee, Andrew, Van Dijk, Marten, Devadas, Srinivas
Abstract Background Our goal is to develop a state-of-the-art protein secondary structure predictor, with an intuitive and biophysically-motivated energy model. We treat structure prediction as an...
A Low Cost Solution to Cloning and Authentication Based on a Lightweight Primitive (2007)
Ranasinghe, D. C., Devadas, Srinivas, Cole, Peter Harold
Damith C. Ranasinghe, Srinivas Devadas, and Peter H. Cole
A Low Cost Solution to Cloning and Authentication Based on a Lightweight Primitive (2007)
Ranasinghe, D. C., Devadas, Srinivas, Cole, Peter Harold
Damith C. Ranasinghe, Srinivas Devadas, and Peter H. Cole
Securing Shared Untrusted Storage by using TPM 1.2 Without Requiring a Trusted OS (2007)
Marten Van Dijk, Jonathan Rhodes, Srinivas Devadas
We address the problem of using an untrusted server with a trusted platform module (TPM) to provide trusted storage for a large number of clients, where each client may own and use several different...
Memoization Attacks and Copy Protection in Partitioned Applications (2006)
O'Donnell, Charles W., Dijk, Marten Vn, Devadas, Srinivas
Application source code protection is a major concern for software architects today. Secure platforms have been proposed that protect the secrecy of application algorithms and enforce copy protection...
Memoization Attacks and Copy Protection in Partitioned Applications (2006)
O'Donnell, Charles W., Dijk, Marten Vn, Devadas, Srinivas
Application source code protection is a major concern for software architects today. Secure platforms have been proposed that protect the secrecy of application algorithms and enforce copy protection...
Sarmenta, Luis F. G., Van Dijk, Marten, O'Donnell, Charles W., Rhodes, Jonathan, Devadas, Srinivas
A trusted monotonic counter is a valuable primitive thatenables a wide variety of highly scalable offlineand decentralized applications that would otherwise be prone to replay attacks, including...
Sarmenta, Luis F. G., Van Dijk, Marten, O'Donnell, Charles W., Rhodes, Jonathan, Devadas, Srinivas
A trusted monotonic counter is a valuable primitive thatenables a wide variety of highly scalable offlineand decentralized applications that would otherwise be prone to replay attacks, including...
Knowledge Flow Analysis for Security Protocols (2006)
Torlak, Emina, Van Dijk, Marten, Gassend, Blaise, Jackson, Daniel, Devadas, Srinivas
Knowledge flow analysis offers a simple and flexible way to find flaws in security protocols. A protocol is described by a collection of rules constraining the propagation of knowledge amongst...
A Generalized Two-Phase Analysis of Knowledge Flows in Security Protocols (2006)
Van Dijk, Marten, Torlak, Emina, Gassend, Blaise, Devadas, Srinivas
We introduce knowledge flow analysis, a simple and flexible formalism for checking cryptographic protocols. Knowledge flows provide a uniform language for expressing the actions of principals,...
Virtual Monotonic Counters and Count-Limited Objects using a TPM without a Trusted OS (2006)
Marten Van Dijk, Charles W. O’donnell, Jonathan Rhodes, Srinivas Devadas
A trusted monotonic counter is a valuable primitive that enables a wide variety of highly scalable offline and decentralized applications that would otherwise be prone to replay attacks, including...
Marten Van Dijk, Charles W. O’donnell, Srinivas Devadas
to secure shared untrusted memory.
Knowledge Flow Analysis for Security Protocols (2005)
Torlak, Emina, Van Dijk, Marten, Gassend, Blaise, Jackson, Daniel, Devadas, Srinivas
Knowledge flow analysis offers a simple and flexible way to find flaws in security protocols. A protocol is described by a collection of rules constraining the propagation of knowledge amongst...
Knowledge Flow Analysis for Security Protocols (2005)
Torlak, Emina, Van Dijk, Marten, Gassend, Blaise, Jackson, Daniel, Devadas, Srinivas
Knowledge flow analysis offers a simple and flexible way to find flaws in security protocols. A protocol is described by a collection of rules constraining the propagation of knowledge amongst...
AEGIS: A Single-Chip Secure Processor (2005)
G. Edward Suh, Charles W. O’donnell, Srinivas Devadas
Abstract This article presents the AEGIS secure processor architecture, which enables new applications by ensuring private and authentic program execution even in the face of physical attack. Our...
G. Edward Suh, Charles W. O’donnell, Ishan Sachdev, Srinivas Devadas
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture,...
Towards constant bandwidth overhead integrity checking of untrusted data (2005)
Dwaine Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten Van Dijk, Srinivas Devadas
We present an adaptive tree-log scheme to improve the performance of checking the integrity of arbitrarily-large untrusted data, when using only a small fixed-sized trusted state. Currently, hash...
G. Edward Suh, Charles W. O’donnell, Ishan Sachdev, Srinivas Devadas
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture,...
G. Edward Suh, Charles W. O’donnell, Ishan Sachdev, Srinivas Devadas
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture,...
Towards constant bandwidth overhead integrity checking of untrusted data (2005)
Dwaine Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten Van Dijk, Srinivas Devadas
We present an adaptive tree-log scheme to improve the performance of checking the integrity of arbitrarily-large untrusted data, when using only a small fixed-sized trusted state. Currently, hash...
Abstract Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data (2005)
Dwaine E. Clarke, Srinivas Devadas, Arthur C. Smith, Dwaine E. Clarke
a trace-hash scheme and an adaptive tree-trace scheme to improve the performance of checking the integrity of arbitrarily-large untrusted data, when using only a small fixed-sized trusted state....
AEGIS: A Single-Chip Secure Processor (2005)
Srinivas Devadas, Arthur C. Smith, Gookwon Edward Suh, Gookwon Edward Suh
LIBRARIES ARCHIVES Development of a Programming Model for the AEGIS Secure Processor (2005)
Ishan Sachdev, Srinivas Devadas, Arthur C. Smith, Ishan Sachdev
by
Ishan Sachdev, Srinivas Devadas, Ishan Sachdev
In this thesis, a high level programming model for the AEGIS secure processor is designed and implemented. The AEGIS processor enables developers to create trusted systems, while only needing to...
Secure Program Execution via Dynamic Information Flow Tracking (2004)
G. Edward Suh, Jaewook Lee, Srinivas Devadas
Dynamic information flow tracking is a hardware mechanism to protect programs against malicious attacks by identifying spurious information flows and restricting the usage of spurious information....
Jae W. Lee, Daihyun Lim, Blaise Gassend, G. Edward Suh, Marten Van Dijk, Srinivas Devadas
This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated...
Rate Guarantees and Overload Protection in Input-Queued Switches (2004)
Hari Balakrishnan, Srinivas Devadas, Douglas Ehlert, Arvind Sandburst
Despite increasing bandwidth demand and the significant research and commercial activity in large-scale Terabit routers for multi-gigabit/s links, many current switch designs do not provide adequate...
Rate Guarantees and Overload Protection in Input-Queued Switches (2004)
Hari Balakrishnan, Srinivas Devadas, Douglas Ehlert
Despite increasing bandwidth demand and the significant research and commercial activity in large-scale Terabit routers for multi-gigabit/s links, many current switch designs do not provide adequate...
PUF-based random number generation (2004)
Charles W. O’donnell, G. Edward Suh, Srinivas Devadas
From security to randomized algorithms, there are many existing problems whose solutions are fundamentally based on the assumption that intrinsically pure random number sources exist. Pseudorandom...
Secure Program Execution Via Dynamic Information Flow Tracking (2003)
Suh, G. Edward, Lee, Jaewook, Zhang, David, Devadas, Srinivas
We present a simple architectural mechanism called dynamicinformation flow tracking that can significantly improve thesecurity of computing systems with negligible performanceoverhead. Dynamic...
Secure Program Execution Via Dynamic Information Flow Tracking (2003)
Suh, G. Edward, Lee, Jaewook, Zhang, David, Devadas, Srinivas
We present a simple architectural mechanism called dynamicinformation flow tracking that can significantly improve thesecurity of computing systems with negligible performanceoverhead. Dynamic...
Incremental multiset hash functions and their application to memory integrity checking (2003)
Dwaine Clarke, Srinivas Devadas, Marten Van Dijk, Blaise Gassend, G. Edward Suh
Abstract. We introduce a new cryptographic tool: multiset hash functions. Unlike standard hash functions which take strings as input, multiset hash functions operate on multisets (or sets). They map...
The AEGIS processor architecture for tamperevident and tamper resistant processing (2003)
Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srini Devadas, G. Edward Suh, ...
We describe the architecture of the aegis processor which can be used to build computing systems secure against both physical and software attacks. aegis assumes that the operating system and all...
Caches and Hash Trees for Efficient Memory Integrity Verification (2003)
Blaise Gassend, G. Edward Suh, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified...
Delay-based Circuit Authentication and Applications (2003)
Blaise Gassend, Dwaine Clarke, Marten Dijk, Srinivas Devadas
We describe a technique to reliably identify individual integrated circuits (ICs), based on a prior delay characterization of the IC. We describe a circuit architecture for a key card for which...
Incremental multiset hash functions and their application to memory integrity checking (2003)
Dwaine Clarke, Srinivas Devadas, Marten Van Dijk, Blaise Gassend, G. Edward Suh
Abstract. We introduce a new cryptographic tool: multiset hash functions. Unlike standard hash functions which take strings as input, multiset hash functions operate on multisets (or sets). They map...
Incremental multiset hash functions and their application to memory integrity checking (2003)
Dwaine Clarke, Srinivas Devadas, Marten Van Dijk, Blaise Gassend, G. Edward, Suh Mit, ...
Abstract. We introduce a new cryptographic tool: multiset hash functions. Unlike standard hash functions which take strings as input, multiset hash functions operate on multisets (or sets). They map...
Efficient Memory Integrity Verification and Encryption for Secure Processors (2003)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks....
Incremental multiset hash functions and their application to memory integrity checking (2003)
Dwaine Clarke, Srinivas Devadas, Marten Van Dijk, Blaise Gassend, G. Edward, Suh Mit, ...
Abstract. We introduce a new cryptographic tool: multiset hash functions. Unlike standard hash functions which take strings as input, multiset hash functions operate on multisets (or sets). They map...
Caches and Hash Trees for Efficient Memory Integrity Verification (2003)
Blaise Gassend, G. Edward Suh, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified...
Aegis: architecture for tamper-evident and tamper-resistant processing (2003)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
{suh,declarke,gassend,marten,devadas} @ mit.edu We describe the architecture for a single-chip AEGIS processor which can be used to build computing systems secure against both physical and software...
Incremental multiset hash functions and their application to memory integrity checking (2003)
Dwaine Clarke, Srinivas Devadas, Marten Van Dijk, Blaise Gassend, G. Edward Suh
Abstract. We introduce a new cryptographic tool: multiset hash functions. Unlike standard hash functions which take strings as input, multiset hash functions operate on multisets (or sets). They map...
Aegis: architecture for tamper-evident and tamper-resistant processing (2003)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all...
Techniques for Accurate Performance Evaluation in Architecture Exploration (2003)
George Hadjiyiannis, Srinivas Devadas
Abstract--- We present a system that automatically generates
Efficient Memory Integrity Verification and Encryption for Secure Processors (2003)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks....
The AEGIS Processor Architecture for Tamper-Evident and Tamper-Resistant Processing (2003)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all...
Incremental Multiset Hash Functions and their Application to Memory Integrity Checking (2003)
Dwaine Clarke, Srinivas Devadas, Marten Van Dijk, Blaise Gassend, G. Edward Suh
We introduce a new cryptographic tool: multiset hash functions. Unlike standard hash functions which take strings as input, multiset hash functions operate on multisets (or sets). They map multisets...
Techniques for Accurate Performance Evaluation in Architecture Exploration (2003)
George Hadjiyiannis, Srinivas Devadas
We present a system that automatically generates a cycle-accurate and bit-true instruction level simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS...
Aegis: architecture for tamper-evident and tamper-resistant processing (2003)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all...
ABSTRACT Secure Program Execution via Dynamic Information Flow Tracking (2003)
Edward Suh, Jaewook Lee, Srini Devadas, David Zhang, G. Edward Suh, Jae W. Lee, ...
We present a simple architectural mechanism called dynamic information flow tracking that can significantly improve the security of computing systems with negligible performance overhead. Dynamic...
Aegis: architecture for tamper-evident and tamper-resistant processing (2003)
G. Edward Suh, G. Edward Suh, Dwaine Clarke, Dwaine Clarke, Blaise Gassend, Blaise Gassend, ...
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all...
Blaise Gassend, Dwaine Clarke, Daihyun Lim, Marten Van Dijk, Srini Devadas, Blaise Gassend, ...
This paper describes a technique to reliably and securely identify individual integrated circuits (ICs) based on the precise measurement of circuit delays and a simple challengeresponse protocol....
Efficient Memory Integrity Verification and Encryption for Secure Processors (2003)
Srini Devadas, G. Edward Suh, G. Edward Suh, Dwaine Clarke, Dwaine Clarke, Blaise Gassend, ...
Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks....
Speeding up Exponentiation using an Untrusted Computational Resource (2003)
Dwaine Clarke, Dwaine Clarke, Srinivas Devadas, Srinivas Devadas, Marten Van Dijk, Marten Van Dijk, ...
Abstract. We present protocols for speeding up fixed-base exponentiation and variablebase exponentiation using an untrusted computation resource. In the fixed-base protocols, the base and exponent...
Caches and Hash Trees for Efficient Memory Integrity Verification (2003)
Blaise Gassend, G. Edward Suh, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified...
6.823 Computer System Architecture, Spring 2002 (2002)
Asanovic, Krste, Arvind, V., Devadas, Srinivas, Hoe, James C. (James Chu-Yue)
Emphasizes the relationship among technology, hardware organization, and programming systems in the evolution of computer architecture. Pipelined, out-of-order, and speculative execution....
6.823 Computer System Architecture, Spring 2002 (2002)
Asanovic, Krste, Arvind, V., Devadas, Srinivas, Hoe, James C. (James Chu-Yue)
Emphasizes the relationship among technology, hardware organization, and programming systems in the evolution of computer architecture. Pipelined, out-of-order, and speculative execution....
Controlled physical random functions (2002)
Blaise Gassend, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs...
A new memory monitoring scheme for memory-aware scheduling and partitioning (2002)
G. Edward Suh, Srinivas Devadas, Larry Rudolph
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters indicate the marginal gain in cache hits as the size of the cache is increased,...
Offline integrity checking of untrusted storage (2002)
Dwaine Clarke, Blaise Gassend, G. Edward Suh, Marten Van Dijk, Srinivas Devadas
We extend the o#ine memory correctness checking scheme presented by Blum et. al [BEG
Silicon Physical Random Functions (2002)
Blaise Gassend, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
We describe the notion of a Physical Random Function (PUF). We argue that a complex integrated circuit can be viewed as a silicon PUF and describe a technique to identify and authenticate individual...
Controlled physical random functions (2002)
Blaise Gassend, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs...
Access-controlled resource discovery for pervasive networks (2002)
Sanjay Raman, Dwaine Clarke, Matt Burnside, Srinivas Devadas, Ronald Rivest
Networks of the future will be characterized by a variety of computational devices that display a level of dynamism not seen in traditional wired networks. Because of the dynamic nature of these...
Hardware mechanisms for memory integrity checking (2002)
G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
Memory integrity verification is a useful primitive when implementing secure processors that are resistant to attacks on hardware components. This paper proposes new hardware schemes to verify the...
Access-controlled resource discovery for pervasive networks (2002)
Sanjay Raman, Dwaine Clarke, Matt Burnside, Srinivas Devadas, Ronald Rivest
Networks of the future will be characterized by a variety of computational devices that display a level of dynamism not seen in traditional wired networks. Because of the dynamic nature of these...
Offline integrity checking of untrusted storage (2002)
Dwaine Clarke, Blaise Gassend, G. Edward Suh, Marten Van Dijk, Srinivas Devadas
We extend the offline memory correctness checking scheme presented by Blum et. al [BEG + 91] to develop an offline checker that can detect attacks by active adversaries. We introduce the concept of...
Secure hardware processors using silicon physical one-way functions (2002)
Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srinivas Devadas
Introduction: Physical one way functions (POWF) are functions that combine an input value with the state of a physical system to produce an output value. In addition, they have in common with...
The Untrusted Computer Problem and Camera-Based Authentication (2002)
Matt Burnside, Dwaine Clarke, Blaise Gassend, Thomas Kotwal, Marten Van Dijk, Srinivas Devadas, ...
The use of computers in public places is increasingly common in everyday life. In using one of these computers, a user is trusting it to correctly carry out her orders. For many transactions,...
Blaise Gassend, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
A Physical Unknown Function (PUF) is a function that is easy to evaluate but hard to characterize. We introduce controlled physical unknown functions (CPUFs) which are PUFs that can only be accessed...
A new memory monitoring scheme for memory-aware scheduling and partitioning (2002)
G. Edward Suh, Srinivas Devadas, Larry Rudolph
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the number of hits from...
Proxy-based security protocols in networked mobile devices (2002)
Matthew Burnside, Dwaine Clarke, Todd Mills, Srinivas Devadas, Ronald Rivest
We describe a resource discovery and communication system designed for security and privacy. All objects in the system, e.g., appliances, wearable gadgets, software agents, and users have associated...
Access-controlled resource discovery for pervasive networks (2002)
Sanjay Raman, Dwaine Clarke, Matt Burnside, Srinivas Devadas, Ronald Rivest
Networks of the future will be characterized by avariety of computational devices that display a level of dynamism not seen in traditional wired networks. Because of the dynamic nature of these...
The Untrusted Computer Problem and Camera-Based Authentication (2002)
Dwaine Clarke, Blaise Gassend, Thomas Kotwal, Matt Burnside, Marten Van Dijk, Srinivas Devadas, ...
Abstract. The use of computers in public places is increasingly common in everyday life. In using one of these computers, a user is trusting it to correctly carry out her orders. For many...
Controlled physical random functions (2002)
Marten Van Dijk, Blaise Gassend, Blaise Gassend, Dwaine Clarke, Dwaine Clarke, ...
A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs...
Access-controlled resource discovery for pervasive networks (2002)
Matthew Burnside, Srini Devadas, Ron Rivest, Sanjay Raman, Sanjay Raman, Dwaine Clarke, ...
Networks of the future will be characterized by avariety of computational devices that display a level of dynamism not seen in traditional wired networks. Because of the dynamic nature of these...
Proxy-based security protocols in networked mobile devices (2002)
Matthew Burnside, Dwaine Clarke, Todd Mills, Andrew Maywah, Srinivas Devadas, Ronald Rivest
Introduction: The goals of ubiquitous and pervasive computing [1, 2] are becoming more and more feasible as the number of computing resources 1 in the world increases rapidly. However, there are...
Proxy-based security protocols in networked mobile devices (2002)
Matthew Burnside, Matthew Burnside, Dwaine Clarke, Dwaine Clarke, Todd Mills, Todd Mills, ...
We describe aresource discovery and communication system designed forsecurity and privacy. All objects in the system, e.g., appliances, wearable gadgets, software agents, and users have associated...
Controlled physical random functions (2002)
Blaise Gassend, Dwaine Clarke, Marten Van Dijk, Srinivas Devadas
A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs...
6.170 Laboratory in Software Engineering, Fall 2001 (2001)
Jackson, Daniel, Devadas, Srinivas
Introduces concepts and techniques relevant to the production of large software systems. Students taught a programming method based on the recognition and description of useful abstractions. Topics:...
6.170 Laboratory in Software Engineering, Fall 2001 (2001)
Jackson, Daniel, Devadas, Srinivas
Introduces concepts and techniques relevant to the production of large software systems. Students taught a programming method based on the recognition and description of useful abstractions. Topics:...
A proxy-based architecture for secure networked wearable devices (2001)
Todd Mills, Matthew Burnside, John Ankcorn, Srinivas Devadas
We describe the software and hardware architecture for a wearable communicator, and a secure protocol for communication between it and its software proxy. The proxy runs on a fast computer so it is...
Dynamic Cache Partitioning for Simultaneous Multithreading Systems (2001)
G. Edward Suh, Larry Rudolph, Srinivas Devadas
This paper proposes a dynamic cache partitioning method for simultaneous multithreading systems. We present a general partitioning scheme that can be applied to setassociative caches at any partition...
Effects of memory performance on parallel job scheduling (2001)
G. Edward Suh, Larry Rudolph, Srinivas Devadas
Abstract. We develop a new metric for job scheduling that includes the effects of memory contention amongst simultaneously-executing jobs that share a given level of memory. Rather than assuming each...
Analytical Cache Models with Applications to Cache Partitioning (2001)
G. Edward Suh, Srinivas Devadas, Larry Rudolph
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache missrate of a multiprocessing system with any cache size and time quanta. The...
SoftwareAssisted Cache Replacement Mechanisms for Embedded Systems (2001)
Prabhat Jain, Srinivas Devadas, Daniel Engels, Larry Rudolph
We address the problem of improving cache predictability and performance in embedded systems through the use of softwareassisted replacement mechanisms. These mechanisms require additional software...
SoftwareAssisted Cache Replacement Mechanisms for Embedded Systems (2001)
Prabhat Jain, Prabhat Jain, Srinivas Devadas, Srinivas Devadas
We address the problem of improving cache predictability (worst-case performance) and performance in embedded systems through the use of software-assisted replacement mechanisms. These mechanisms...
Effects of memory performance on parallel job scheduling (2001)
G. Edward Suh, Larry Rudolph, Srinivas Devadas
Abstract. We develop a new metric for job scheduling that includes the effects of memory contention amongst simultaneously-executing jobs that share a given level of memory. Rather than assuming each...
Prabhat Jain, Srini Devadas, Larry Rudolph, Prabhat Jain, Srinivas Devadas, Larry Rudolph
Aggressive prefetch methods can suffer from cache pollution when prefetched data replaces useful data in the cache, causing performance degradation. In this paper, we present a methodology that...
Analytical Cache Models with Applications to Cache Partitioning (2001)
G. Edward Suh, Srinivas Devadas, Larry Rudolph
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache missrate of a multiprocessing system with any cache size and time quanta. The...
Scheduler-Based Prefetching for Multilevel Memories (2001)
Derek Chiou, Srinivas Devadas, Josh Jacobs, Prabhat Jain, Vinson Lee, Enoch Peserico, ...
Memory latency is a significant bottleneck in modern computing systems. With few exceptions, the process/thread/task currently running on the CPU implicitly owns all caches and main memory....
Enoch Peserico, Srinivas Devadas, Larry Rudolph, G. Edward Suh, Enoch Peserico, Srinivas Devadas, ...
When multiple applications have to time-share limited physical memory resources, they can incur significant performance degradation at the beginning of their respective time slices due to page...
E ects of Memory Performance on Parallel Job Scheduling (2001)
Larry Rudolph, Srinivas Devadas, G. Edward Suh, Larry Rudolph, Srinivas Devadas
Abstract. We develop a new metric for job scheduling that includes the e ects of memory contention amongst simultaneously-executing jobs that share a given level of memory. Rather than assuming each...
Analytical Cache Models with Applications to Cache Partitioning (2001)
G. Edward Suh, Srinivas Devadas, Srinivas Devadas, Larry Rudolph, Larry Rudolph
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache missrate of a multiprocessing system with any cache size and time quanta. The...
Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (2000)
Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas
We propose a way to improve the performance of embedded processors running data-intensive applications by allowing software to allocate on-chip memory on an application-specific basis. Onchip memory...
Observability analysis of embedded software for Coverage-Directed validation (2000)
Jose C. Costa, Srinivas Devadas, Jose C. Monteiro
The most common approach to checking correctness of a hardware or software design is to verify that a description of the design has the proper behavior as elicited by a series of input stimuli. In...
Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (2000)
Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas
We propose a way to improve the performance of embedded processors running data-intensive applications by allowing software to allocate on-chip memory on an applicationspecific basis. On-chip memory...
Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (2000)
Derek Chiou, Derek Chiou, Prabhat Jain, Prabhat Jain, Srinivas Devadas, Srinivas Devadas, ...
We propose a methodology to improve the performance of embedded processors running data-intensive applications by allowing embedded software to manage on-chip memory on an application-specific or...
Dynamic Cache Partitioning via Columnization (2000)
Derek Chiou, Derek Chiouy, Larry Rudolph, Larry Rudolphy, Srinivas Devadas, Srinivas Devadasy, ...
This paper introduces column caching, a flexible mechanism that allows software to dynamically customize cache behavior through fine-grain control of its placement policy. For a set-associative...
Observability Analysis of Embedded Software for Coverage-Directed Validation (2000)
Jos Costa Srinivas, José C. Costa, Srinivas Devadas, José C. Monteiro
Syntax Tree (AST) of a C program. The AST can then be manipulated in several ways such as adding or deleting nodes in it. Finally, after changing the AST, the c2c tool produces the C program for that...
Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (2000)
Derek Chiou, Derek Chiou, Derek Chiou, Prabhat Jain, Prabhat Jain, Prabhat Jain, ...
We propose a methodology to improve the performance of embedded processors running data-intensive applications by allowing embedded software to manage on-chip memory on an application-specific or...
Dynamic cache partitioning via columnization (2000)
Derek Chiou, Srinivas Devadas, Larry Rudolph, Boon S. Ang, Derek Chiouy, Derek Chiouy, ...
This paper introduces column caching, a exible mechanism that allows software to dynamically customize cache behavior through ne-grain control of its placement policy. For a set-associative cache,...
Observability analysis of embedded software for Coverage-Directed validation (2000)
José C. Costa, Srinivas Devadas, José C. Monteiro
The most common approach to checking correctness of a hardware or software design is to verify that a description of the design has the proper behavior as elicited by a series of input stimuli. In...
Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches (2000)
Derek Chiou, Derek Chiou, Prabhat Jain, Prabhat Jain, Srinivas Devadas, Srinivas Devadas, ...
We propose a methodology to improve the performance of embedded processors running data-intensive applications by allowing embedded software to manage on-chip memory on an application-specific or...
A methodology for accurate performance evaluation in architecture exploration (1999)
George Hadjiyiannis, Srinivas Devadas
We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS...
Farzan Fallah, Pranav Ashar, Srinivas Devadas
Validation of RTL circuits remains the primary bottleneck in improving designturnaround time, and simulation remains the primary methodology for validation. Simulation-based validation has suffered...
A Methodology for Accurate Performance Evaluation in Architecture Exploration (1999)
George Hadjiyiannis, Pierro Russo, Srinivas Devadas
We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS...
Critical Problems in Very Large Scale Computer Systems. (1998)
Agarwal, Anant, Dally, William J., Devadas, Srinivas
The research vehicle for this contract is the largest possible computer that could be conceived for the mid to late 1990s. The technical challenges of such a machine serve as the guiding stimulus for...
Critical Problems in Very Large Scale Computer Systems. (1998)
Agarwal, Anant, Dally, William J., Devadas, Srinivas
The research vehicle for this contract is the largest p ossible computer that could be conceived for the mid to late 1990s. The technical challenges of such a machine serve as the guiding stimulus...
General Decomposition of Sequential Machines: Relationships to State Assignment, (1998)
In this paper, we present new techniques for state assignment of finite state machines based on state machine decomposition algorithms. A finite state machine can be decomposed into smaller...
Approaches to Multi-Level Sequential Logic Synthesis, (1998)
This paper presents approaches to multi-level sequential logic synthesis-algorithms and techniques for the area and performance optimization of interconnected finite state machine descriptions....
Easily Testable PLA-Based Finite State Machines. (1998)
Devadas, Srinivas, Ma, Hi-Keung T., Newton, A. R.
This paper outlines a synthesis procedure, which beginning from a State Transition Graph description of a sequential machine, produces an optimized easily testable PLA-based logic implementation....
Delay Test Generation for Synchronous Sequential Circuits, (1998)
We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than...
Redundancies and Don't Cares in Sequential Logic Synthesis. (1998)
Devadas, Srinivas, Ma, Hi-Keung T., Newton, A. R.
The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test...
Test Generation for Highly Sequential Circuits. (1998)
Ghosh, Abhijit, Devadas, Srinivas, Newton, A. R.
We address the problem of generating test sequences for stuck-at faults in non-scan synchronous sequential circuits. We present a novel test procedure that exploits both the structure of the...
Critical Problems in Very Large Scale Computer Systems. (1998)
Agarwal, Anant, Dally, William J., Devadas, Srinivas, Leighton, F. T.
The research vehicle for this contract is the largest possible computer that could be conceived for the mid to late 1990's. The technical challenges of such a machine serve as our guiding stimulus...
Optimal Layout via Boolean Satisfiability. (1998)
Most optimization problems in layout have been shown to be NP-complete, resulting in researchers abandoning the search for optimum solutions even for small-scale problem instances. In this paper we...
Optimum and Heuristic Algorithms for Finite State Machine Decomposition and Partitioning. (1998)
Ashar, Pravnav, Devadas, Srinivas, Newton, A. R.
Techniques have been proposed in the past for various types of finite state machine (FSM) decomposition that use the number of states or edges in the decomposed circuits as the cost function to be...
Devadas, Srinivas, Keutzer, Kurt
In this paper we continue to investigate the impact of logic synthesis on the testability of sequential circuits that can be modeled as finite state machines. Complete testability of a sequential...
Irredundant Sequential Machines Via Optimal Logic Synthesis, (1998)
Devadas, Srinivas, Ma, Hi-Keung T., Newton, A. R., Sangiovanni-Vincentelli, A.
It is well known that optimal logic synthesis can ensure fully testable combinational logic design. In this paper we show that optimal sequential logic synthesis can produce irredundant, fully...
A Unified Approach to the Synthesis of Fully Testable Sequential Machines, (1998)
Devadas, Srinivas, Keutzer, Kurt
In this paper we attempt to unify and extend the various approaches to synthesizing fully testable sequential circuits that can be modeled as finite state machines (FSMs). We first identify classes...
Exact Algorithms for Output Encoding, State Assignment and Four-Level Boolean Minimization, (1998)
Devadas, Srinivas, Newton, A. R.
In this paper we present efficient, exact algorithms for the problems of output encoding, state assignment and four-level Boolean minimization. All previous automatic approaches to encoding problems...
Critical Problems in Very Large Scale Computer Systems. (1998)
Agarwal, Anant, Dally, William J., Devadas, Srinivas, Leighton, F. T.
The research vehicle for this contract is the largest possible computer that can be conceived for the mid to late 1990's. We call this machine an American Resource Computer or ARC. We imagine this...
Critical Problems in Very Large Scale Computer Systems. (1998)
Agarwal, Anant, Dally, William J., Devadas, Srinivas, Leighton, F. T.
The research vehicle for this contract is the largest possible computer than can be conceived for the mid to late 1990's. We call this machine an 'American Resource Computer' or 'ARC'. We imagine...
Silvina Hanono, Srinivas Devadas
The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures. AVIV optimizes for minimum code size. Retargetable code...
Silvina Hanono, Srinivas Devadas
The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures. AVIV optimizes for minimum code size. Retargetable code...
Functional vector generation for HDL models using linear programming and 3-satisfiability (1998)
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally...
Instruction Selection, Resource Allocation, and Scheduling in the (1998)
Retargetable Code Generator, Silvina Hanono, Srinivas Devadas
The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures. AVIV optimizes for minimum code size. Retargetable code...
Farzan Fallah Srinivas, Srinivas Devadas, Kurt Keutzer
Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally...
Functional Vector Generation for HDL models Using Linear Programming and 3-Satisfiability (1998)
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally...
A Low Power, Low Bandwidth Protocol for Remote Wireless Terminals (1998)
George Hadjiyiannis, Anantha Chandrakasan, Srinivas Devadas
We present a low bandwidth protocol for wireless multi-media terminals targetedtowards low power consumption on the terminal side. With the widespread use of portable computing devices, low power has...
A Low Power, Low Bandwidth Protocol for Remote Wireless Terminals (1998)
George Hadjiyiannis, Anantha Chandrakasan, Srinivas Devadas
We present a low bandwidth protocol for wireless multi-media terminals targeted towards low power consumption on the terminal side. With the widespread use of portable computing devices, low power...
Silvina Hanono, Srinivas Devadas
The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures. AVIV optimizes for minimum code size. Retargetable code...
Functional vector generation for HDL models using linear programming and 3-satisfiability (1998)
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally...
Devadas, \BDD-based synthesis of extended burst-mode controllers (1998)
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
Abstract — We examine the implications of a new hazard-free combinational logic synthesis method [1], which generates multiplexor-based networks from binary decision diagrams (BDDs) —...
Switching Activity Estimation using Limited Depth Reconvergent Path Analysis (1997)
José C. Costa, José C. Monteiro, Srinivas Devadas
We describe a method of polynomial simulation to calculate switching activities in a general-delay combinational logic circuit. This method is a generalization of the exact signal probability...
Solving Covering Problems Using LPR-Based Lower Bounds (1997)
Abstract---Unate and binate covering problems are a special class of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization...
Analysis and Evaluation of Address Arithmetic Capabilities (1997)
Ashok Sudarsanam, Stan Liao, Srinivas Devadas
Abstract---Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexed addressing...
Switching Activity Estimation using Limited Depth Reconvergent Path Analysis (1997)
Jose C. Costa, Jose C. Monteiro, Srinivas Devadas
We describe a method of polynomial simulation to calculate switching activities in a general-delay combinational logic circuit. This method is a generalization of the exact signal probability...
Analysis and Evaluation of Address Arithmetic Capabilities (1997)
Ashok Sudarsanam, Stan Liao, Srinivas Devadas
Abstract—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexed addressing...
Solving Covering Problems Using LPR-Based Lower Bounds (1997)
Abstract—Unate and binate covering problems are a special class of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization...
ISDL: An Instruction Set Description Language for Retargetability (1997)
George Hadjiyiannis, Silvina Hanono, Srinivas Devadas
We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features and flexibility of ISDL enable...
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures (1997)
Ashok Sudarsanam, Stan Liao, Srinivas Devadas
Many embedded architectures provide indirect addressing modes with autoincrement /decrement arithmetic. Since these architectures generally do not feature an indexed addressing mode, automatic...
Solving Covering Problems Using LPR-Based Lower Bounds (1997)
Abstract—Unate and binate covering problems are a special class of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization...
Scheduling Techniques to Enable Power Management (1996)
José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
“Shut-down ” techniques are effective in reducing the power dissipation of logic circuits. Recently, methods have been developed that identify conditions under which the output of a module in a...
Scheduling Techniques to Enable Power Management (1996)
Jos E Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
"Shut-down " techniques are effective in reducing the power dissipation of logic circuits. Recently, methods have been developed that identify conditions under which the output of a...
An observability-based code coverage metric for functional simulation (1996)
Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
Abstract--- Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the designer...
A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits (1996)
Srinivas Devadas, José Carlos, José Carlos, Alves Pereira Monteiro
Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption...
Code optimization techniques for embedded DSP microprocessors (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
Abstract—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code...
Storage Assignment to Decrease Code Size (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose...
A low power, low bandwidth protocol for remote wireless terminals (1995)
George Hadjiyiannis, Anantha Chandrakasan, Srinivas Devadas
We present a low bandwidth protocol for wireless multi-media terminals targeted towards low power consumption on the terminal side. With the widespread use of portable computing devices, low power...
We describe a new method for directly synthesizing a hazard-free multilevel logic implementation from a given logic specification. The method is based on free/ordered Binary Decision Diagrams...
Code density optimization for embedded DSP processors using data compression techniques (1995)
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
We address the problem of code size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systems. We use data compression methods to...
Instruction selection using binate covering for code size optimization (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang
Abstract---We address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation...
Storage Assignment to Decrease Code Size (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose...
Storage Assignment to Decrease Code Size (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose...
Instruction Selection Using Binate Covering for Code Size Optimization (1995)
Stan Liao Srinivas, Srinivas Devadas, Kurt Keutzer, Steve Tjiang
We address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation methods...
Code Optimization Techniques for Embedded DSP Microprocessors (1995)
Stan Liao Srinivas, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g. those in the TMS320 series) have highly irregular datapaths, and conventional code generation...
Probabilistic Manipulation of Boolean Functions Using Free Boolean Diagrams (1995)
Amelia Shen Srinivas, Srinivas Devadas, Abhijit Ghosh
We propose a data structure for Boolean functions termed the Free Boolean Diagram. A Free Boolean Diagram allows decision vertices as in the conventional Binary Decision Diagram, but also allows...
Challenges in Code Generation For Embedded Processors (1995)
Peter Marwedel, Gert Goossens, Guido Araujo, Srinivas Devadas, Sharad Malik, Kurt Keutzer, ...
The emergence of integrated circuits in which both the program-ROM and the processor are integrated on a single die initiates a new era of problems for programming language compilers. In such a...
José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and power dissipation,...
Power Estimation for Sequential Logic Circuits (1995)
Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
Recently developed methods for power estimation have primarily focused on combinational logic. In this paper, we present a framework for the efficient and accurate estimation of average power...
Code Generation And Optimization Techniques For Embedded Digital Signal Processors (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, ...
Introduction The advent of 0.5¯ processing that allows for the integration of 5 million transistors on a single integrated circuit has brought forth new challenges and opportunities in...
Code Optimization Techniques for Embedded DSP Microprocessors (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation...
José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and power dissipation,...
Exact and Approximate Methods for Switching Activity Estimation in Sequential Logic Circuits (1994)
Chi-ying Tsui, Massoud Pedram, Alvin M. Despain, Srinivas Devadas, Bill Lin
Recently developed methods for power estimation have primarily focused on combinational logic. In this paper, we present a framework for the efficient and accurate estimation of average power...
Performance-driven Synthesis of Asynchronous Controllers (1994)
Kenneth Y. Yun, Bill Lin, David L. Dill, S. Devadas, Srinivas Devadas
We examine the implications of a new hazard-free combinational logic synthesis method [10], which generates multiplexor-based networks from binary decision diagrams (BDDs) --- representations of...
Bitwise Encoding of Finite State Machines (1994)
José Monteiro, James Kukula, Srinivas Devadas, Horácio Neto
We propose an innovative method of encoding the states of finite state machines. Our approach consists of iteratively defining the code word, one bit at a time. In each iteration the input state...
José Monteiro, Srinivas Devadas
We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable...
Precomputation-Based Sequential Logic Optimization for Low Power (1994)
For Low Power, Mazhar Alidina, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output...
Precomputation-Based Sequential Logic Optimization for Low Power (1994)
For Low Power, Mazhar Alidina, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output...
Precomputation-Based Sequential Logic Optimization for Low Power (1994)
For Low Power, José Monteiro, Mazhar Alidina, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output...
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (1994)
Jos'e Monteiro, Srinivas Devadas, Bill Lin
We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a non-linear system of equations of size N , where the...
Precomputation-Based Sequential Logic Optimization for Low Power (1994)
For Low Power, Mazhar Alidina, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output...
José Monteiro, Srinivas Devadas
this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out...
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (1994)
José Monteiro, Srinivas Devadas, Bill Lin
We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a non-linear system of equations of size N, where the...
Retiming sequential circuits for low power (1993)
José Monteiro, Srinivas Devadas
Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately...
Boolean factorization using multiple-valued minimization (1993)
Stan Liao, Srinivas Devadas, Abhijit Ghosh
We show that the problem of factoring a sum-ofproducts representation of a logic function can be transformed into one of multiple-valued prime generation followed by branch-and-bound covering. We...
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms (1993)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
Delay computation in combinational logic circuits is complicated by the existence of unsensitizable (false) paths and this problem is arising with increasing frequency in circuits produced by...
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms (1993)
Srinivas Devadas, Kurt Keutzer, Sharad Malik
This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be...
Boolean Factorization Using Multiple-Valued Minimization (1993)
Stan Liao, Srinivas Devadas, Abhijit Ghosh
We show that the problem of factoring a sum-ofproducts representation of a logic function can be transformed into one of multiple-valued prime generation followed by branch-and-bound covering. We...
Retiming Sequential Circuits for Low Power (1993)
José Monteiro, Srinivas Devadas, Abhijit Ghosh
Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately...
Analysis and Design of Regular Structures for Robust Dynamic Fault Testability (1993)
Michael J. Bryan, Srinivas Devadas, Kurt Keutzer
Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening...
Estimation of Average Switching Activity in Combinational and Sequential Circuits (1992)
Abhiiit Ghosh, Srinivas Devadas, Kurt Keutzer Jacob
We address the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays...
Synthesis of Robust Delay-Fault Testable Circuits: Theory (1992)
Srinivas Devadas, Kurt Keutzer
Correct operation of synchronous digital circuits requires propagation delays of all sensitizable paths in the circuit to be smaller than a specified limit. Physical defects and processing variations...
Techniques for optimization-based synthesis of digital systems /--by Srinivas Devadas. (1988)
Memorandum No. UCB/ERL M88/54.
Learning biophysically-motivated parameters for alpha helix prediction
Gassend, Blaise, O'Donnell, Charles W, Thies, William, Lee, Andrew, Van Dijk, Marten, Devadas, Srinivas
Efficient Algorithms for Probing the RNA Mutation Landscape
Waldispühl, Jérôme, Devadas, Srinivas, Berger, Bonnie, Clote, Peter
The diversity and importance of the role played by RNAs in the regulation and development of the cell are now well-known and well-documented. This broad range of functions is achieved through...
RNAmutants: a web server to explore the mutational landscape of RNA secondary structures
Waldispühl, Jerome, Devadas, Srinivas, Berger, Bonnie, Clote, Peter
The history and mechanism of molecular evolution in DNA have been greatly elucidated by contributions from genetics, probability theory and bioinformatics—indeed, mathematical developments such as...
Efficient stochastic simulation of reaction–diffusion processes via direct compilation
Lis, Mieszko, Artyomov, Maxim N., Devadas, Srinivas, Chakraborty, Arup K.
We present the Stochastic Simulator Compiler (SSC), a tool for exact stochastic simulations of well-mixed and spatially heterogeneous systems. SSC is the first tool to allow a readable high-level...